應屆畢業生
學歷不限
2025-04-22 08:32:55
10777人關注
職位描述
該職位還未進行加V認證，請仔細了解后再進行投遞！
崗位職責:
1.RTL synthesis, SDC/UPF verification, low power design implementation for advanced technology chips.
2.Design flow/methodology development and innovation for front-end design challenges.
3.Be responsible for RTL verification, synthesis, low power design, and STA/timing closure works for customer’s projects and internal system test chips.
任職要求:
1.MS or above in EE, CS related fields. Experience in Digital IC design flow (from Synthesis, DFT, MBIST, Formality, STA), RTL design, RTL verification is plus.
2.New graduate or 3 years working experience.
3.Familiar with EE CAD tool such as Design compiler, DFT complier, MBIST, n-Lint, Verdi, Verilog tools/flows.
4.Familiar with tcl/Perl/Python program.
1.RTL synthesis, SDC/UPF verification, low power design implementation for advanced technology chips.
2.Design flow/methodology development and innovation for front-end design challenges.
3.Be responsible for RTL verification, synthesis, low power design, and STA/timing closure works for customer’s projects and internal system test chips.
任職要求:
1.MS or above in EE, CS related fields. Experience in Digital IC design flow (from Synthesis, DFT, MBIST, Formality, STA), RTL design, RTL verification is plus.
2.New graduate or 3 years working experience.
3.Familiar with EE CAD tool such as Design compiler, DFT complier, MBIST, n-Lint, Verdi, Verilog tools/flows.
4.Familiar with tcl/Perl/Python program.
注：聯系我時，請說是在河南人才網上看到的。
工作地點
地址：漯河郾城區九龍湖國際企業總部
求職提示：用人單位發布虛假招聘信息，或以任何名義向求職者收取財物（如體檢費、置裝費、押金、服裝費、培訓費、身份證、畢業證等），均涉嫌違法，請求職者務必提高警惕。
職位發布者
HR
臺積電(南京)有限公司
-
電子技術·半導體·集成電路
-
200-499人
-
外商獨資·外企辦事處
-
浦口經濟開發區紫峰路16號
